(1) Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, in particular to a nonvolatile semiconductor storage device which enables a less expensive LSI tester to perform a redundancy repair judgment test thereof.
(2) Description of the Prior Art
The configuration as well as the testing method of a conventional nonvolatile semiconductor storage device will be described referring to FIGS. 1 and 2.
FIG. 1 is a block diagram showing a conventional nonvolatile semiconductor storage device, and FIG. 2 is a flowchart showing a wafer test for the conventional nonvolatile semiconductor storage device.
In FIG. 1, a reference numeral 31 designates an address buffer; 32 a bit-line decoder; 33 a word-line decoder; 34 a memory cell array; 35 an I/O gate; 36 a writing/erasing high-voltage switch; 37 a write-state machine; 38 a status register; 39 an output multiplexer; 40 an input buffer; 41 an output buffer; and 42 a write state machine control algorithm (program) storing section. Writing/erasing high-voltage switch 36 is a voltage switching circuit that selectively outputs high voltages required for writing and erasing. Write state machine 37 is a control circuit that controls writing and erasing operations in accordance with the algorithms stored in control algorithm storing section 42.
As stated above, FIG. 2 is a flowchart showing a wafer test for a conventional nonvolatile semiconductor storage device. The repair judgment test (test 1: writing test, test 2: erasing test, test 3: reading test) is performed for all the memory cells in memory cell array 34, and the result for each is stored into the defect information storing memory in the tester. In the repair routine, the address having a fault stored in the defect information storing memory is analyzed, and if it is repairable, its repair is effected. In the confirmation test, if it is judged as `good`, the next test will be effected.
However, in the above conventional method, the LSI tester needs to have a defect information storing memory for storing address information of faulty memory cells therein. Accordingly, the LSI tester becomes costly, increasing cost for testing.